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Bernard Tourancheau

Professeur Université Grenoble Alpes (Joseph Fourier)


Bernard Tourancheau got MSc in Apply Maths from Grenoble University in 1986 and a MSc in Renewable Energy Science and Technology from Loughborough University in 2007. He was awarded best Computer Science PhD by Institut National Polytechnique of Grenoble in 1989 for his work on Parallel Computing for Distributed Memory Architectures.
Working for the LIP laboratory, he was appointed assistant professor at Ecole Normale Supérieure de Lyon in 1989 before joining CNRS as a Senior Researcher. After initiating a CNRS-NSF collaboration, he worked two and half years on leave at the University of Tennessee on a senior researcher position with the US Center for Research in Parallel Computation at the ICL laboratory.
He then took a Professor position at University of Lyon in 1995 where he created a research laboratory and the INRIA EPI RESO, specialized in High Speed Networking and HPC Clusters.
In 2001, he joined SUN Microsystems Laboratories for a 6 years sabbatical as a Principal Investigator in the DARPA HPCS project where he lead the backplane networking group.
Back in academia he oriented his research on sensor and actuator networks for building energy efficiency at LIP and CITI labs and associated INRIA EPI.
He was appointed Professor at University Joseph Fourier of Grenoble in 2012. Since then, he is developing research at the LIG laboratory Drakkar team about protocols and architectures for sensor networks and their applications to energy efficiency in buildings as well as GPGPU algorithms’ optimization.
He has authored more than an hundred peer-reviewed publications and owns 8 patents.


Recent publications

All publications.

2017

auteur
Minh-Quan Ho, Christian Obrecht, Bernard Tourancheau, Benoît Dupont de Dinechin, Julien Hascoet
titre
Improving 3D Lattice Boltzmann Method stencil with asynchronous transfers on many-core processors
article
36th IEEE International Performance Computing and Communications Conference (IPCCC 2017), Dec 2017, San Diego, United States
Accès au texte intégral et bibtex
http://hal.univ-grenoble-alpes.fr/hal-01652614/file/opal_async_HAL.pdf BibTex
auteur
Mališa Vučinić, Michał Król, † Baptiste Jonglez, Titouan Coladon, Bernard Tourancheau
titre
Trickle-D: High Fairness and Low Transmission Load with Dynamic Redundancy
article
IEEE Internet of Things Journal, IEEE, 2017
Accès au texte intégral et bibtex
https://hal.archives-ouvertes.fr/hal-01653203/file/trickle-dynamic-HAL.pdf BibTex
auteur
Timothy Claeys, Franck Rousseau, Bernard Tourancheau
titre
Securing Complex IoT Platforms with Token Based Access Control and Authenticated Key Establishment
article
International Workshop on Secure Internet of Things (SIoT), Sep 2017, Oslo, Norway. ESORICS Workshops. 〈http://siot-workshop.org〉
Accès au bibtex
BibTex
auteur
Timothy Claeys, Franck Rousseau, Bernard Tourancheau, Andrzej Duda
titre
Clock Drift Prediction for Fast Rejoin in 802.15.4e TSCH Networks
article
26th International Conference on Computer Communication and Networks (ICCCN), Jul 2017, Vancouver, BC, Canada. 2017, 26th International Conference on Computer Communication and Networks (ICCCN). 〈10.1109/ICCCN.2017.8038401〉
Accès au bibtex
BibTex

2015

auteur
Minh-Quan Ho, Bernard Tourancheau, Christian Obrecht, Benoît Dupont de Dinechin, Jérôme Reybert
titre
MPI communication on MPPA Many-core NoC: design, modeling and performance issues
article
ParCo 2015, Sep 2015, Edinburgh, United Kingdom. Advances in Parallel Computing, Volume 27: Parallel Computing: On the Road to Exascale, 2016, 〈http://www.parco2015.org/〉. 〈10.3233/978-1-61499-621-7-113〉
Accès au texte intégral et bibtex
http://hal.univ-grenoble-alpes.fr/hal-01398190/file/mppampi_article.pdf BibTex
auteur
Malisa Vucinic, Bernard Tourancheau, Franck Rousseau, Andrzej Duda, Laurent Damon, Roberto Guizzetti
titre
OSCAR: Object security architecture for the Internet of Things
article
Ad Hoc Networks, Elsevier, 2015, 32, pp.3-16. 〈10.1016/j.adhoc.2014.12.005〉
Accès au bibtex
BibTex

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